LAYOUT COMPACTION

VLSI DESIGN INTRODUCTION

Large no of devices.
Optimization requirements for high performance.

Area.
Speed. Power dissipation. Design time. Testability.

VLSI DESIGN CYCLE

1. 2. 3. 4. 5. 6. 7. 8. System specification Functional design Logic design Circuit design Physical design Design verification Fabrication Packaging, testing, and debugging

PHYSICAL DESIGN
Converts a circuit description into a geometric description. This description is used for fabrication of the chip. Basic steps in the physical design cycle: Partitioning Floorplanning and placement Routing Compaction

i. ii. iii. iv.

PHYSICAL DESIGN IN DETAIL

LAYOUT COMPACTION
After P&R, the layout is functionally complete. Some vacant space may still be present in the layout. Due to non-optimality of P&R Compaction = removing vacant space Improves cost, performance, and yield Key for high-performance full-custom layouts Standard cells only channel heights may be minimized But channel compactors are near-optimal

Compaction tries to minimize total layout area while Retaining speed Respecting violating design rules and designer-specified constraints Three ways to minimize the layout area

Reducing inter-feature space

Reducing feature size
Check size rules

Check spacing design rules

Reshaping features

Electrical connectivity must be preserved

DESIGN RULES
Interface between Design Engineer and Process Engineer Guidelines for constructing process masks Unit dimension: Minimum line width Scalable design rules: lambda parameter Absolute dimensions (micron rules)

PROCESS LAYERS

Compaction Algorithms
Based on minimum distance between features
Constraint graph based Virtual grid based

Based on direction of movement of features

1-D Compaction 1 D Compaction 2-D Compaction

Constraint Graph Based Compaction

Constraint graph G = (V,E) Each vertex v represents a component. V The set of edges (E) represents constraints.

Connectivity Constraints
If two features X and Y are required to be within a
distance s of each other. A physical connection can be represented in the graph as a pair of edges between X and Y, each with weight s.

Separation Constraints
Two features X and Y are required to be at least d units apart from each other. Represented as an edge from X to Y of weight d.

Example

Virtual Grid Based Compaction

This method assumes that the layout is to be drawn on a grid. Each component is considered attached to a grid line. The compaction operation compresses the grid along with all components placed on it keeping the grid lines straight along the way. The minimum distance between two adjacent grid lines depends on the components on these gridlines. X-compaction is followed by Y-compaction. Advantage: Simple and easy to implement. Disadvantage: Does not produce compact layouts as compared to the constraint graph method.

Example

2- Dimensional Compaction
2-D compaction is in general much better than performing 1-D compaction. 2-D compaction, if solved optimally, produces minimum-area layouts. It is very time consuming. Thus 1-D compaction techniques have been proposed. Perform x-direction compaction moves while making small moves in the y-direction.

Example

1-Dimensional Compaction
A deterministic algorithm.

Key idea is to provide enough lateral movements to blocks during compaction to resolve interferences. This is called 1-dimensional compactor, since the geometry is not as free as in true 2dimensional compaction. The algorithm maintains an X-Y adjacency graph.
Vertices represent blocks. Edges represent horizontal and vertical adjacency.

 Two blocks have a horizontal edge if they share a vertical boundary. Two blocks have a vertical edge if they share a horizontal boundary. The labels on the edges represent the minimum allowable distance between blocks. Four additional vertices are added to keep all the blocks within the required bounded rectangle. Free space is ignored in computing the neighborhood edges between blocks The algorithm assumes that the input is a partially completed layout, obtained by two applications of a 1-D compactor.

Maintains two lists floor and ceiling. Floor consists of all the blocks which are visible from the top, and may become a neighbor of future block. Ceiling is a list of all blocks which can be moved immediately (namely, those which are visible from the bottom). Selects the lowest block in the ceiling list and moves it to the place on the floor which maximizes the gap between floor and ceiling. The process is continued until all blocks are moved from ceiling to floor.

Layout Constraints
For a given layout instance, all features may be described by a set of placement constraints These layout constraints are imposed by design rules Min spacing (separation) design rules

Expressing constraints

 Goal of 1-D compaction is to generate a minimum width layout. Determination of minimum width is equivalent to solving a longest path problem. The longest path from source to a vertex is the coordinate of the vertex. In practical layouts, the constraints graphs are very local. Most edges represent very local constraints in the layout. Theoretically, run time is O(|V|+|E|) Practically, run time is close to linear in |V|, the size of the layout!

Compute the longest path in a graph G = <V,E,constraints,Origin> (constraints is a set of labels, Origin is the super-source of the DAG) Forward-prop(W){ for each vertex v in W for each edge <v,w> from v value(w) = max(value(w), value(v) + value(w) + constraint(<v,w>)) if all incoming edges of w have been traversed add w to W } Longest path(G) Forward_prop(Origin) }

Compute the longest path in a graph G = <V, E, constraints, ,Origin> (constraints is a set of labels, Origin is the super-source of the DAG) Forward-prop(W) { for each vertex v in W for each edge <v,w> from v value(w) = max(value(w), value(v) + value(w) + constraint(<v,w>)) if all incoming edges of w have been traversed add w to W } Longest path(G) Forward_prop(Origin) }

Compute the longest path in a graph G = <V,E,constraints,Origin> (constraints is a set of labels, Origin is the super-source of the DAG) Forward-prop(W){ for each vertex v in W for each edge <v,w> from v value(w) = max(value(w), value(v) + value(w) + constraint(<v,w>)) if all incoming edges of w have been traversed add w to W } Longest path(G) Forward_prop(Origin) }

Compute the longest path in a graph G = <V,E,constraints,Origin> (constraints is a set of labels, Origin is the super-source of the DAG) Forward-prop(W){ for each vertex v in W for each edge <v,w> from v value(w) = max(value(w), value(v) + value(w) + constraint(<v,w>)) if all incoming edges of w have been traversed add w to W } Longest path(G) Forward_prop(Origin) }

Compute the longest path in a graph G = <V,E,constraints,Origin> (constraints is a set of labels, Origin is the super-source of the DAG) Forward-prop(W){ for each vertex v in W for each edge <v,w> from v value(w) = max(value(w), value(v) + value(w) + constraint(<v,w>)) if all incoming edges of w have been traversed add w to W } Longest path(G) Forward_prop(Origin) }

References
Algorithms for VLSI Design AutomationSabih H.Gerez Layout compaction - Prof. A. R. Newton Prof. Kurt Keutzer www.wikipedia.com www.gigapedia.com

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