80486 Microprocessor

Features
The 32-bit 80486 is the next evolutionary step up

from the 80386

One of the most obvious feature included in a 80486

is a built in math coprocessor. This coprocessor is essentially the same as the 80387 processor used with a 80386, but being integrated on the chip allows it to execute math instructions about three times as fast as a 80386/387 combination

 80486 is an 8Kbyte code and data cache

To make room for the additional signals, the 80486

is packaged in a 168 pin, pin grid array package instead of the 132 pin PGA used for the 80386.

EFLAG Register Of The 80486

CF: Carry Flag AF: Auxiliary carry ZF: Zero Flag SF : Sign Flag TF : Trap Flag IE : Interrupt Enable DF : Direct Flag OF : Over Flow IOPL : I/O Privilege Level NT : Nested Task Flag RF : Resume Flag VM : Virtual Mode AC : Alignment Check

 AC flag is set whenever there is an access to a

misaligned address, a fault is generated

Misaligned address means a word access to an odd

address or a double word access to an address that is not on a double word boundary

80586 PENTIUM- Features

Superscalar Architecture

Super pipelined
Dynamic Branch prediction Pipelined Floating Point Unit

Separate 8k Code and 8k data caches

Similar to 80486 but with 64-bit data bus Wider internal data paths: 128- and 256-bit wide

Superscalar performance allows two instructions per

clock cycle

 So far intel CPU upto 8486-has one instruction is

issued to the execution unit per sec To improve this, architects employs the technique of Multiple Instruction Issue (MII) To achieve this CPU must have more than one execution channels .there exists two problems A)How to issue multiple instructions B) How to execute them concurrently

 MII architecture may be again redivided into two

architectures A)Very Long Instruction Word (VLIW)architecture B)Superscalar architecture

In VLIW processor ,the compiler reorders the sequential

stream of code that is coming from memory into a fixed size instruction group and issues them in parallel for execution In super scalar the hardware decides which instructions are to be issued concurrently at run time

Pentium Architecture

Scalar Execution
CPU issues two instructions in parallel to the two

independent integer pipelines known as U and V pipelines Each of this have 5 stage pipelines branch prediction done using the branch target buffer (BTB) the pipelined floating-point unit, and the 64-bit external data bus Even-parity checking is implemented for the data bus and the internal RAM arrays (caches and TLBs).

Cache & Floating Point Unit

Unlike 80486 ,80586 has separate code and data

cache each of size 8kbyte 80486 has a FPU without pipelining,80586 has eight stage pipeline. First 5 are same as U and V integer pipeline There are 8 general purpose floating point registers in FPU In the opcode fetch stage ,the FPU fetches the operands either from the cache or the FP registers

Floating point Unit

FRD - Floating Point Rounding

FDD - Floating Point Division FADD - Floating Point Addition FEXP - Floating Point Exponent FAND - Floating Point And FMUL - Floating Point Multiply

Pentium PRO and Pentium II

Pentium Pro has small significant changes over the

basic architecture of pentium One of the constraints in the pentium is that it obeys a linear instruction sequencing i.e instructions pass through fetch, decode and execute stages sequentially To over come this optimized scheduling algorithm may be used where the CPU may look ahead for other instructions and speculatively execute them

 One such optimum and intelligent dynamic

execution strategy has been adopted in PentiumPro microprocessor. It uses twelve stages pipelined with U and V pipes

Optimized scheduling (Dynamic Execution of Instruction)

There are 3 important concepts

1. Speculative Execution means CPU should speculate which of the next instructions can be executed earlier 2. Dual Independent Bus Pentium pro uses two independent buses --One between CPU and Memory and -- Other between CPU and the cache memory 3. Multiple Branch prediction

Implementation of the Dynamic Instruction Execution Scheme

To speculate instruction execution ,processor look

ahead of a pool of instructions and execute some of these next instruction ahead of time It looks 20-30 instruction a head Out of these 25% may be are of branch instruction So if processor execute next instruction ahead there exists a probability that results may go wrong So the CPU stores these results in the invisible registers temporarily.

 Pentium pro incorporates three independent engines

a) Fetch-decode unit b) Dispatch-execute unit c) Retire Unit

 Fetch-decode unit - it accepts the sequence of

instruction from cache memory(speculative fetching) Three parallel decoding unit decodes the instructions into micro operations Micro operations contains two logical sources and one logical destination which are stored in Register Alias Table (RAT) RAT translates logical reference into the physical register set Micro operations were sent instruction pool

 Dispatch- execute unit- it does scheduling of the

instruction by determining the dependencies after which it is executed Speculative results are stored temporarily Retire unit- removes the micro operations which have been executed from the instruction pool

Features of Pentium III

Pentium III is suitable for applications like imaging,

image processing, speech processing, multimedia and internet application PIII-incorporates multiple branch prediction algorithm New instruction supporting advanced imaging, speech and multimedia applications Dual independent bus architecture increases bandwidth A 512 kbytes unified,2 level caches